riscemu.instructions package
Submodules
- riscemu.instructions.RV32A module
RV32ARV32A.instruction_lr_w()RV32A.instruction_sc_w()RV32A.instruction_amoswap_w()RV32A.instruction_amoadd_w()RV32A.instruction_amoand_w()RV32A.instruction_amoor_w()RV32A.instruction_amoxor_w()RV32A.instruction_amomax_w()RV32A.instruction_amomaxu_w()RV32A.instruction_amomin_w()RV32A.instruction_amominu_w()
- riscemu.instructions.RV32F module
RV32FRV32F.instruction_fmadd_s()RV32F.instruction_fmsub_s()RV32F.instruction_fnmsub_s()RV32F.instruction_fnmadd_s()RV32F.instruction_fadd_s()RV32F.instruction_fsub_s()RV32F.instruction_fmul_s()RV32F.instruction_fdiv_s()RV32F.instruction_fsqrt_s()RV32F.instruction_fsgnj_s()RV32F.instruction_fsgnjn_s()RV32F.instruction_fsgnjx_s()RV32F.instruction_fmin_s()RV32F.instruction_fmax_s()RV32F.instruction_fcvt_w_s()RV32F.instruction_fcvt_wu_s()RV32F.instruction_fmv_x_w()RV32F.instruction_feq_s()RV32F.instruction_flt_s()RV32F.instruction_fle_s()RV32F.instruction_fclass_s()RV32F.instruction_fcvt_s_w()RV32F.instruction_fcvt_s_wu()RV32F.instruction_fmv_w_x()RV32F.instruction_flw()RV32F.instruction_fsw()RV32F.parse_rd_rs()RV32F.parse_rd_rs_rs()RV32F.parse_rd_rs_rs_rs()
- riscemu.instructions.RV32I module
RV32IRV32I.instruction_lb()RV32I.instruction_lh()RV32I.instruction_lw()RV32I.instruction_lbu()RV32I.instruction_lhu()RV32I.instruction_sb()RV32I.instruction_sh()RV32I.instruction_sw()RV32I.instruction_sll()RV32I.instruction_slli()RV32I.instruction_srl()RV32I.instruction_srli()RV32I.instruction_sra()RV32I.instruction_srai()RV32I.instruction_add()RV32I.instruction_addi()RV32I.instruction_sub()RV32I.instruction_lui()RV32I.instruction_auipc()RV32I.instruction_xor()RV32I.instruction_xori()RV32I.instruction_or()RV32I.instruction_ori()RV32I.instruction_and()RV32I.instruction_andi()RV32I.instruction_slt()RV32I.instruction_slti()RV32I.instruction_sltu()RV32I.instruction_sltiu()RV32I.instruction_beq()RV32I.instruction_bne()RV32I.instruction_blt()RV32I.instruction_bge()RV32I.instruction_bltu()RV32I.instruction_bgeu()RV32I.instruction_j()RV32I.instruction_jal()RV32I.instruction_jalr()RV32I.instruction_ret()RV32I.instruction_ecall()RV32I.instruction_ebreak()RV32I.instruction_scall()RV32I.instruction_sbreak()RV32I.instruction_nop()RV32I.instruction_li()RV32I.instruction_la()RV32I.instruction_mv()
- riscemu.instructions.RV32M module
- riscemu.instructions.RV_Debug module
- riscemu.instructions.instruction_set module
InstructionSetInstructionSet.__init__()InstructionSet.load()InstructionSet.get_instructions()InstructionSet.parse_mem_ins()InstructionSet.parse_rd_rs_rs()InstructionSet.parse_rd_rs_imm()InstructionSet.parse_rs_rs_imm()InstructionSet.get_reg_content()InstructionSet.pcInstructionSet.mmuInstructionSet.regs
Module contents
RiscEmu (c) 2021 Anton Lydike
SPDX-License-Identifier: MIT
This package holds all instruction sets, available to the processor