riscemu.priv package

Submodules

• riscemu.priv.CSR module
  • CSR
    • CSR.mstatus_cache_dirty
    • CSR.__init__()
    • CSR.regs
    • CSR.listeners
    • CSR.virtual_regs
    • CSR.mstatus_cache
    • CSR.set()
    • CSR.get()
    • CSR.set_listener()
    • CSR.set_mstatus()
    • CSR.get_mstatus()
    • CSR.callback()
    • CSR.assert_can_read()
    • CSR.assert_can_write()
    • CSR.virtual_register()
    • CSR.dump_mstatus()
• riscemu.priv.CSRConsts module
  • MCAUSE_TRANSLATION
  • MSTATUS_OFFSETS
  • MSTATUS_LEN_2
  • CSR_NAME_TO_ADDR
• riscemu.priv.ElfLoader module
  • ElfBinaryFileLoader
    • ElfBinaryFileLoader.__init__()
    • ElfBinaryFileLoader.program
    • ElfBinaryFileLoader.can_parse()
    • ElfBinaryFileLoader.get_options()
    • ElfBinaryFileLoader.parse()
• riscemu.priv.Exceptions module
  • CpuTrapType
    • CpuTrapType.TIMER
    • CpuTrapType.SOFTWARE
    • CpuTrapType.EXTERNAL
    • CpuTrapType.EXCEPTION
  • CpuTrap
    • CpuTrap.__init__()
    • CpuTrap.interrupt
    • CpuTrap.code
    • CpuTrap.mtval
    • CpuTrap.priv
    • CpuTrap.type
    • CpuTrap.mcause
    • CpuTrap.message()
  • IllegalInstructionTrap
    • IllegalInstructionTrap.__init__()
    • IllegalInstructionTrap.code
    • IllegalInstructionTrap.interrupt
    • IllegalInstructionTrap.mtval
    • IllegalInstructionTrap.type
    • IllegalInstructionTrap.priv
  • InstructionAddressMisalignedTrap
    • InstructionAddressMisalignedTrap.__init__()
    • InstructionAddressMisalignedTrap.code
    • InstructionAddressMisalignedTrap.interrupt
    • InstructionAddressMisalignedTrap.mtval
    • InstructionAddressMisalignedTrap.type
    • InstructionAddressMisalignedTrap.priv
  • InstructionAccessFault
    • InstructionAccessFault.__init__()
    • InstructionAccessFault.code
    • InstructionAccessFault.interrupt
    • InstructionAccessFault.mtval
    • InstructionAccessFault.type
    • InstructionAccessFault.priv
  • TimerInterrupt
    • TimerInterrupt.__init__()
    • TimerInterrupt.code
    • TimerInterrupt.interrupt
    • TimerInterrupt.mtval
    • TimerInterrupt.type
    • TimerInterrupt.priv
  • EcallTrap
    • EcallTrap.__init__()
    • EcallTrap.code
    • EcallTrap.interrupt
    • EcallTrap.mtval
    • EcallTrap.type
    • EcallTrap.priv
  • InvalidElfException
    • InvalidElfException.__init__()
    • InvalidElfException.message()
  • LoadAccessFault
    • LoadAccessFault.code
    • LoadAccessFault.interrupt
    • LoadAccessFault.mtval
    • LoadAccessFault.type
    • LoadAccessFault.priv
    • LoadAccessFault.__init__()
    • LoadAccessFault.message()
• riscemu.priv.ImageLoader module
  • MemoryImageLoader
    • MemoryImageLoader.can_parse()
    • MemoryImageLoader.get_options()
    • MemoryImageLoader.parse()
    • MemoryImageLoader.parse_no_debug()
    • MemoryImageLoader.instantiate()
• riscemu.priv.PrivCPU module
  • PrivCPU
    • PrivCPU.csr
    • PrivCPU.__init__()
    • PrivCPU.pending_traps
    • PrivCPU.TIME_RESOLUTION_NS
    • PrivCPU.run()
    • PrivCPU.launch()
    • PrivCPU.load_program()
    • PrivCPU.step()
    • PrivCPU.show_perf()
    • PrivCPU.record_perf_profile()
    • PrivCPU.get_loaders()
• riscemu.priv.PrivMMU module
  • PrivMMU
    • PrivMMU.get_sec_containing()
    • PrivMMU.global_instruction_context()
    • PrivMMU.sections
    • PrivMMU.programs
    • PrivMMU.global_symbols
• riscemu.priv.PrivRV32I module
  • PrivRV32I
    • PrivRV32I.cpu
    • PrivRV32I.instruction_csrrw()
    • PrivRV32I.instruction_csrrs()
    • PrivRV32I.instruction_csrrc()
    • PrivRV32I.instruction_csrrsi()
    • PrivRV32I.instruction_csrrwi()
    • PrivRV32I.instruction_csrrci()
    • PrivRV32I.instruction_mret()
    • PrivRV32I.instruction_uret()
    • PrivRV32I.instruction_sret()
    • PrivRV32I.instruction_scall()
    • PrivRV32I.instruction_beq()
    • PrivRV32I.instruction_bne()
    • PrivRV32I.instruction_blt()
    • PrivRV32I.instruction_bge()
    • PrivRV32I.instruction_bltu()
    • PrivRV32I.instruction_bgeu()
    • PrivRV32I.instruction_j()
    • PrivRV32I.instruction_jal()
    • PrivRV32I.instruction_jalr()
    • PrivRV32I.instruction_sbreak()
    • PrivRV32I.parse_crs_ins()
    • PrivRV32I.parse_mem_ins()
• riscemu.priv.privmodes module
  • PrivModes
    • PrivModes.USER
    • PrivModes.SUPER
    • PrivModes.MACHINE
• riscemu.priv.types module
  • ElfInstruction
    • ElfInstruction.name
    • ElfInstruction.args
    • ElfInstruction.encoded
    • ElfInstruction.get_imm()
    • ElfInstruction.get_imm_reg()
    • ElfInstruction.get_reg()
    • ElfInstruction.__init__()
  • ElfMemorySection
    • ElfMemorySection.__init__()
    • ElfMemorySection.read_ins()
    • ElfMemorySection.write()
    • ElfMemorySection.end
    • ElfMemorySection.name
    • ElfMemorySection.flags
    • ElfMemorySection.size
    • ElfMemorySection.base
    • ElfMemorySection.owner
    • ElfMemorySection.context
  • MemoryImageDebugInfos
    • MemoryImageDebugInfos.VERSION
    • MemoryImageDebugInfos.__init__()
    • MemoryImageDebugInfos.sections
    • MemoryImageDebugInfos.symbols
    • MemoryImageDebugInfos.globals
    • MemoryImageDebugInfos.base
    • MemoryImageDebugInfos.serialize()
    • MemoryImageDebugInfos.load()
    • MemoryImageDebugInfos.builder()

Module contents

RiscEmu (c) 2021 Anton Lydike

SPDX-License-Identifier: MIT

The priv Module holds everything necessary for emulating privileged risc-v assembly

Running priv is only preferable to the normal userspace emulator, if you actually want to emulate the whole system.

Syscalls will have to be intercepted by your assembly code.

The PrivCPU Implements the Risc-V M/U Model, meaning there is machine mode and user mode. No PMP or paging is available.