riscemu.priv.Exceptions module

class riscemu.priv.Exceptions.CpuTrapType(value)

Bases: Enum

An enumeration.

TIMER = 1

SOFTWARE = 2

EXTERNAL = 3

EXCEPTION = 4

exception riscemu.priv.Exceptions.CpuTrap(code: int, mtval, type: CpuTrapType, priv: PrivModes = PrivModes.MACHINE)

Bases: BaseException

__init__(code: int, mtval, type: CpuTrapType, priv: PrivModes = PrivModes.MACHINE)

interrupt: int

The isInterrupt bit in the mstatus register

code: int

31-bit value encoding the exception code in the mstatus register

mtval: UInt32

contents of the mtval register

priv: PrivModes

The privilege level this trap targets

type: CpuTrapType

The type (timer, external, software) of the trap

property mcause

message() → str

exception riscemu.priv.Exceptions.IllegalInstructionTrap(ins: ElfInstruction)

Bases: CpuTrap

__init__(ins: ElfInstruction)

code: int

31-bit value encoding the exception code in the mstatus register

interrupt: int

The isInterrupt bit in the mstatus register

mtval: UInt32

contents of the mtval register

type: CpuTrapType

The type (timer, external, software) of the trap

priv: PrivModes

The privilege level this trap targets

exception riscemu.priv.Exceptions.InstructionAddressMisalignedTrap(addr: int)

Bases: CpuTrap

__init__(addr: int)

code: int

31-bit value encoding the exception code in the mstatus register

interrupt: int

The isInterrupt bit in the mstatus register

mtval: UInt32

contents of the mtval register

type: CpuTrapType

The type (timer, external, software) of the trap

priv: PrivModes

The privilege level this trap targets

exception riscemu.priv.Exceptions.InstructionAccessFault(addr: int)

Bases: CpuTrap

__init__(addr: int)

code: int

31-bit value encoding the exception code in the mstatus register

interrupt: int

The isInterrupt bit in the mstatus register

mtval: UInt32

contents of the mtval register

type: CpuTrapType

The type (timer, external, software) of the trap

priv: PrivModes

The privilege level this trap targets

exception riscemu.priv.Exceptions.TimerInterrupt

Bases: CpuTrap

__init__()

code: int

31-bit value encoding the exception code in the mstatus register

interrupt: int

The isInterrupt bit in the mstatus register

mtval: UInt32

contents of the mtval register

type: CpuTrapType

The type (timer, external, software) of the trap

priv: PrivModes

The privilege level this trap targets

exception riscemu.priv.Exceptions.EcallTrap(mode: PrivModes)

Bases: CpuTrap

__init__(mode: PrivModes)

code: int

31-bit value encoding the exception code in the mstatus register

interrupt: int

The isInterrupt bit in the mstatus register

mtval: UInt32

contents of the mtval register

type: CpuTrapType

The type (timer, external, software) of the trap

priv: PrivModes

The privilege level this trap targets

exception riscemu.priv.Exceptions.InvalidElfException(msg: str)

Bases: RiscemuBaseException

__init__(msg: str)

message()

exception riscemu.priv.Exceptions.LoadAccessFault(msg, addr, size, op)

Bases: CpuTrap

code: int

31-bit value encoding the exception code in the mstatus register

interrupt: int

The isInterrupt bit in the mstatus register

mtval: UInt32

contents of the mtval register

type: CpuTrapType

The type (timer, external, software) of the trap

priv: PrivModes

The privilege level this trap targets

__init__(msg, addr, size, op)

message()