riscemu.priv.PrivCPU module

RiscEmu (c) 2021 Anton Lydike

SPDX-License-Identifier: MIT

class riscemu.priv.PrivCPU.PrivCPU(conf)

Bases: CPU

This is a CPU that has different modes, instruction sets and registers.

It should support M and U Mode, but no U-Mode Traps.

This is meant to emulate whole operating systems.

csr: CSR

Reference to the control and status registers

__init__(conf)

pending_traps: List[CpuTrap]

A list of traps which are pending to be handled

TIME_RESOLUTION_NS: int = 10000000

controls the resolution of the time csr register (in nanoseconds)

run(verbose=False)

launch(program: Optional[Program] = None, verbose: bool = False)

load_program(program: Program)

step(verbose=True)

show_perf()

record_perf_profile()

classmethod get_loaders() → Iterable[Type[ProgramLoader]]