riscemu.priv.CSR module

class riscemu.priv.CSR.CSR

Bases: object

This holds all Control and Status Registers (CSR)

mstatus_cache_dirty = True

__init__()

regs: Dict[int, UInt32]

All Control and Status Registers are stored here

listeners: Dict[int, Callable[[UInt32, UInt32], None]]

virtual_regs: Dict[int, Callable[[], UInt32]]

list of virtual CSR registers, with values computed on read

mstatus_cache: Dict[str, UInt32]

set(addr: Union[str, int], val: Union[int, UInt32])

get(addr: Union[str, int]) → UInt32

set_listener(addr: Union[str, int], listener: Callable[[UInt32, UInt32], None])

set_mstatus(name: str, val: UInt32)

Set mstatus bits using this helper. mstatus is a 32 bit register, holding various machine status flags Setting them by hand is super painful, so this helper allows you to set specific bits.

Please make sure your supplied value has the correct width!

Parameters:

• name –

• val –

Returns:

get_mstatus(name) → UInt32

callback(addr: Union[str, int])

assert_can_read(mode: PrivModes, addr: int)

assert_can_write(mode: PrivModes, addr: int)

virtual_register(addr: Union[str, int])

dump_mstatus()