riscemu.priv.CSRConsts module

riscemu.priv.CSRConsts.MCAUSE_TRANSLATION: Dict[Tuple[int, int], str] = {(0, 0): 'Instruction address misaligned', (0, 1): 'Instruction access fault', (0, 2): 'Illegal instruction', (0, 3): 'Breakpoint', (0, 4): 'Load address misaligned', (0, 5): 'Load access fault', (0, 6): 'Store/AMO address misaligned', (0, 7): 'Store/AMO access fault', (0, 8): 'environment call from user mode', (0, 9): 'environment call from supervisor mode', (0, 11): 'environment call from machine mode', (0, 12): 'Instruction page fault', (0, 13): 'Load page fault', (0, 15): 'Store/AMO page fault', (1, 0): 'User software interrupt', (1, 1): 'Supervisor software interrupt', (1, 3): 'Machine software interrupt', (1, 4): 'User timer interrupt', (1, 5): 'Supervisor timer interrupt', (1, 7): 'Machine timer interrupt', (1, 8): 'User external interrupt', (1, 9): 'Supervisor external interrupt', (1, 11): 'Machine external interrupt'}

Assigns tuple (interrupt bit, exception code) to their respective readable names

riscemu.priv.CSRConsts.MSTATUS_OFFSETS: Dict[str, int] = {'fs': 13, 'mie': 3, 'mpie': 7, 'mpp': 11, 'mpriv': 17, 'mxr': 19, 'sd': 31, 'sie': 1, 'spie': 5, 'spp': 8, 'sum': 18, 'tsr': 22, 'tvm': 20, 'tw': 21, 'uie': 0, 'upie': 4, 'xs': 15}

Offsets for all mstatus bits

riscemu.priv.CSRConsts.MSTATUS_LEN_2 = ('mpp', 'fs', 'xs')

All mstatus parts that have length 2. All other mstatus parts have length 1

riscemu.priv.CSRConsts.CSR_NAME_TO_ADDR: Dict[str, int] = {'halt': 1929, 'marchid': 3858, 'mcause': 834, 'mepc': 833, 'mhartid': 3860, 'mie': 772, 'mimpid': 3859, 'mip': 836, 'misa': 769, 'mstatus': 768, 'mtimecmp': 1920, 'mtimecmph': 1921, 'mtval': 835, 'mtvec': 773, 'mvendorid': 3857, 'time': 3073, 'timeh': 3201}

Translation for named registers