riscemu.priv.PrivRV32I module

RiscEmu (c) 2021 Anton Lydike

SPDX-License-Identifier: MIT

class riscemu.priv.PrivRV32I.PrivRV32I(cpu: CPU)

Bases: RV32I

cpu: PrivCPU

This is an extension of RV32I, written for the PrivCPU class

instruction_csrrw(ins: Instruction)

instruction_csrrs(ins: Instruction)

instruction_csrrc(ins: Instruction)

instruction_csrrsi(ins: Instruction)

instruction_csrrwi(ins: Instruction)

instruction_csrrci(ins: Instruction)

instruction_mret(ins: Instruction)

instruction_uret(ins: Instruction)

instruction_sret(ins: Instruction)

instruction_scall(ins: Instruction)

Overwrite the scall from userspace RV32I

instruction_beq(ins: Instruction)

instruction_bne(ins: Instruction)

instruction_blt(ins: Instruction)

instruction_bge(ins: Instruction)

instruction_bltu(ins: Instruction)

instruction_bgeu(ins: Instruction)

instruction_j(ins: Instruction)

instruction_jal(ins: Instruction)

instruction_jalr(ins: Instruction)

instruction_sbreak(ins: Instruction)

parse_crs_ins(ins: Instruction)

parse_mem_ins(ins: Instruction) → Tuple[str, int]

parses both rd, rs, imm and rd, imm(rs) argument format and returns (rd, imm+rs1) (so a register and address tuple for memory instructions)